1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor memory device with silicon-on-insulator (SOI) structure memory cells and to a semiconductor memory device.
2. Description of the Related Art
The structure of a memory cell in a conventional nonvolatile semiconductor memory device has its limits even if an attempt is made to miniaturize the memory cell in dimensions. In a typical case, if the channel length of a memory cell is set to 50 nm or less, the on-off ratio of the channel current decreases due to a short channel effect, with the result that the transistor of the memory cell malfunctions. This causes a problem: semiconductor memory devices cannot be highly integrated.
To overcome this problem, a method of forming memory cells on an SOI crystal has been proposed in recent years (e.g., Jpn. Pat. Appln. KOKAI Publication No. 5-335234, Jpn. Pat. Appln. KOKAI Publication No. 6-333822, or Jpn. Pat. Appln. KOKAI Publication No. 9-036042). However, it is difficult to form on an insulating film a large-area silicon layer with good crystallinity. This contributes to variations in the characteristics from one cell to another. Particularly in an SOI-structure element formed by solid-phase-epitaxial growth, the surface of non-conformity whose position is uncertain develops on a buried insulating film. This causes a problem: a cell transistor is formed on the non-conforming surface, making the operation unstable.